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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 1.2 / oct. 2007 1 128mb synchronous dram base d on 2m x 4bank x16 i/o document title 4bank x 2m x 16bits synchronous dram revision history revision no. history draft date remark 0.1 initial draft jan. 2007 preliminary 1.0 final version apr. 2007 1. 1 correct typo error page10, page12 july. 2007 1.2 correct typo error page 10 : the note for the parameter ?toh? ( 2 -> blank ) oct. 2007
rev. 1.2 / oct. 2007 2 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series description the hynix hy57v281620f(l/s)tp series is a 134,217,728bit cmos synchronous dram, ideally suited for the memory applications which require wide data i/o and high bandwi dth. hy57v281620 f( l/s)t(p) series is organized as 4banks of 2,097,152 x 16. hy57v281620f(l/s)tp is offering fully synchronous operation refe renced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data pa ths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), an d the burst count sequence(se - quential or interleave). a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or wr ite command on any cycle. (this pipelined design is not re - stricted by a '2n' rule) features ordering information note: 1. HY57V281620FTP series: normal power, lead free. 2. hy57v281620fltp series: low power, lead free. 3. hy57v281620fltp series: su per low power, lead free. 4. hy57v281620fst(p) series: super low po wer; contact hynix for availability 5. hy57v281620f(l/s)t(p)-x: commercial temperature (0 o c to 70 o c ) 6. hy57v281620f(l/s)t(p)-xi: industrial temperature ( -40 o c to 85 o c) part no. clock frequency organization interface package hy57v281620f(l/s)tp-5 200mhz 4banks x 2mbits x16 lvttl 54 pin tsopii hy57v281620f(l/s)tp-6 166mhz hy57v281620f(l/s)tp-7 143mhz hy57v281620f(l/s)tp-h 133mhz ? voltage: vdd, vddq 3.3v supply voltage ? all device pins are compatible with lvttl interface ? 54 pin tsopii (lead free package) ? all inputs and outputs referenced to positive edge of system clock ? data mask function by udqm, ldqm ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency; 2, 3 clocks ? burst read single write operation ? operating temperature - commercial temperature (0 o c to 70 o c) - industrial temperature (-40 o c to 85 o c)
rev. 1.2 / oct. 2007 3 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series pin assign ments vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm /we /cas /ras /cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 54 pin tsopii 400mil x 875mil 0.8mm pin pitch
rev. 1.2 / oct. 2007 4 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series pin description symbol type description clk clock the system clock input. all other in puts are registered to the sdram on the rising edge of clk cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among powe r down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke, udqm and ldqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a11 address row address: ra0 ~ ra11, column address: ca0 ~ ca8 auto-precharge flag: a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details udqm, ldqm data input/output mask controls output buffers in read mo de and masks input data in write mode dq0 ~ dq15 data input/output multiplexed data input / output pin vdd/vss power supply/ground power supply for internal ci rcuits and input buffers vddq/vssq data output power/ground power supply for output buffers nc no connection no connection
rev. 1.2 / oct. 2007 5 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series functional block diagram 2mbit x 4banks x 16 i/o synchronous dram internal row counter column pre decoder column add counter self refresh logic & timer sense amp & i/o gate i/o buffer & logic address register burst counter mode register state machine address buffers bank select column active row active cas latency clk cke cs ras cas we u/ldqm a0 a1 ba1 ba0 a11 row pre decoder refresh dq0 dq15 x-decoder x-decoder x-decoder x-decoder y-decoder 2mx16 bank 0 2mx16 bank 1 2mx16 bank 2 2mx16 bank 3 memory cell array data out control pipe line control
rev. 1.2 / oct. 2007 6 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series basic functional description mode register ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 op code 0 0 cas latency bt burst length op code a9 write mode 0burst read and burst write 1 burst read and single write burst type a3 burst type 0sequential 1interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 00 0 1 1 00 1 2 2 01 0 4 4 01 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved cas latency a6 a 5 a4 cas latency 0 0 0 r e s e r v e d 0 0 1 r e s e r v e d 0 1 0 2 0 1 1 3 1 0 0 r e s e r v e d 1 0 1 r e s e r v e d 1 1 0 r e s e r v e d 1 1 1 r e s e r v e d
rev. 1.2 / oct. 2007 7 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series absolute maximum rating dc operating condition (commercial: ta = 0 o c to 70 o c, industrial: ta = -40 o c to 85 o c) note: 1. all voltages are referenced to vss = 0v 2. vih(max) is acceptable 5.6v ac pulse width with <=3ns of duration. 3. vil(min) is acceptable -2.0v ac pulse width with <=3ns of duration ac operating test condition ( commercial: ta = 0 o c to 70 o c, industrial: ta = -40 o c to 85 o c , vdd=3.3 0.3v, vss=0v) parameter symbol rating unit ambient temperature commercial temperature ta 0 ~ 70 o c industrial temperature -40 ~ 85 storage temperature tstg -55 ~ 125 o c voltage on any pin relative to vss vin, vout -1.0 ~ 4.6 v voltage on vdd relative to vss vdd, vddq -1.0 ~ 4.6 v short circuit output current ios 50 ma power dissipation pd 1 w soldering temperature / time tsolder 260 / 10 o c / sec parameter symbol min. typ max unit note power supply voltage vdd, vddq 3.0 3.3 3.6 v 1 input high voltage vih 2.0 3.0 vddq + 0.3 v 1, 2 input low voltage vil -0.3 - 0.8 v 1, 3 parameter symbol value unit note ac input high / low level voltage vih / vil 2.4 / 0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement cl 50 pf z0 = 50 output output vtt = 1.4v 50pf rt = 50 vtt = 1.4v 50pf dc output load circuit ac output load circuit rt = 500 ? ? ?
rev. 1.2 / oct. 2007 8 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series capacitance ( commercial: ta = 0 o c to 70 o c, industrial: ta = -40 o c to 85 o c , f=1mhz, vdd=3.3v) dc characteristics i ( commercial: ta = 0 o c to 70 o c, industrial: ta = -40 o c to 85 o c) note: 1. v in = 0 to 3.3v, all other balls are not tested under v in =0v 2. d out is disabled, v out =0 to 3.6 parameter pin symbol min max unit input capacitance clk ci1 2.0 4.0 pf a0 ~ a11, ba0, ba1, cke, cs , ras , cas , we , ldqm, udqm ci2 2.5 5.0 pf data input / outp ut capacitance dq0 ~ dq15 ci/o 3.0 5.5 pf parameter symbol min max unit note input leakage current ili -1 1 ua 1 output leakage current ilo -1 1 ua 2 output high voltage voh 2.4 - v ioh = - 2 ma output low voltage vol - 0.4 v iol = + 2 ma
rev. 1.2 / oct. 2007 9 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series dc characteristics ii ( commercial: ta = 0 o c to 70 o c, industrial: ta = -40 o c to 85 o c) note: 1. idd1 and idd4 depend on output loading and cycle ra tes. specified values are measured with the output open 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3. HY57V281620FTP series: normal power hy57v281620fltp series: low power hy57v281620fstp series: super low power parameter symbol test condition speed unit note 5 6 7 h operating current idd1 burst length=1, one bank active trc trc(min), iol=0ma 120 110 100 100 ma 1 precharge standby current in power down mode idd2p cke vil(max), tck = 15ns 2 ma idd2ps cke vil(max), tck = 2 ma precharge standby current in non power down mode idd2n cke vih(min), cs vih(min), tck = 15ns input signals are changed one time dur - ing 2clks. all other pins vdd-0.2v or 0.2v 18 ma idd2ns cke vih(min), tck = input signals are stable. 15 active standby current in power down mode idd3p cke vil(max), tck = 15ns 5 ma idd3ps cke vil(max), tck = 5 active standby current in non power down mode idd3n cke vih(min), cs vih(min), tck = 15ns input signals are changed one time dur - ing 2clks. all other pins vdd-0.2v or 0.2v 40 ma idd3ns cke vih(min), tck = input signals are stable. 35 burst mode operating cur - rent idd4 tck tck(min), iol=0ma all banks active 120 110 100 100 ma 1 auto refresh current idd5 trc trc(min), all banks active 210 200 190 190 ma 2 self refresh current idd6 cke 0.2v normal 2 ma 3 low power 800 ua super low power 500 ua
rev. 1.2 / oct. 2007 10 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series ac characteristics i (ac operating conditions unless otherwise noted) note: 1. assume tr / tf (input rise and fall time) is 1ns. if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter. 2. access time to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0 v. if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter. parameter sym - bol 5 6 7 h unit note min max min max min max min max system clock cycle time cl = 3 tck3 5.0 1000 6.0 1000 7.0 1000 7.5 100 0 ns cl = 2 tck2 10 10 10 10 ns clock high pulse width tchw 1.75 - 2.0 - 2.0 - 2.5 - ns 1 clock low pulse width tclw 1.75 - 2.0 - 2.0 - 2.5 - ns 1 access time from clock cl = 3 tac3 - 4.5 - 5.4 - 5.4 - 5.4 ns 2 cl = 2 tac2 - 6.0 - 6.0 - 6.0 - 6.0 ns data-out hold time toh 2.0 - 2.0 - 2.5 - 2.7 - ns data-input setup time tds 1.5 - 1.5 - 1.5 - 1.5 - ns 1 data-input hold time tdh 0.8 - 0.8 - 0.8 - 0.8 - ns 1 address setup time tas 1.5 - 1.5 - 1.5 - 1.5 - ns 1 address hold time tah 0.8 - 0.8 - 0.8 - 0.8 - ns 1 cke setup time tcks 1.5 - 1.5 - 1.5 - 1.5 - ns 1 cke hold time tckh 0.8 - 0.8 - 0.8 - 0.8 - ns 1 command setup time tcs 1.5 - 1.5 - 1.5 - 1.5 - ns 1 command hold time tch 0.8 - 0.8 - 0.8 - 0.8 - ns 1 clk to data output in low-z time tolz 1.0 - 1.0 - 1.5 - 1.5 - ns clk to data output in high-z time cl = 3 tohz3 - 4.5 - 5.4 - 5.4 - 5.4 ns cl = 2 tohz2 - 6.0 - 6.0 - 6.0 - 6.0 ns
rev. 1.2 / oct. 2007 11 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series ac characteristics ii (ac operating conditions unless otherwise noted) note: 1. a new command can be given trrc after self refresh exit. parameter symbol 5 6 7 h unit note min max min max min max min max ras cycle time operation trc 55 - 60 - 63 - 63 - ns ras cycle time auto refresh trrc 55 - 60 - 63 - 63 - ns ras to cas delay trcd 15 - 18 - 20 - 20 - ns ras active time tras 38.7 100k 42 100k 42 100k 4 2 120 k ns ras precharge time trp 15 - 18 - 20 - 20 - ns ras to ras bank active delay trrd 10 - 12 - 14 - 15 - ns cas to cas delay tccd 1 - 1 - 1 - 1 - clk write command to data-in delay twtl 0 - 0 - 0 - 0 - clk data-in to precharge command tdpl 2 - 2 - 2 - 2 - clk data-in to active command tdal tdpl + trp dqm to data-out hi-z tdqz 2 - 2 - 2 - 2 - clk dqm to data-in mask tdqm 0 - 0 - 0 - 0 - clk mrs to new command tmrd 2 - 2 - 2 - 2 - clk precharge to data output high-z cl = 3 tproz3 3 - 3 - 3 - 3 - clk cl = 2 tproz2 2 - 2 - 2 - 2 - clk power down exit time tdpe 1 - 1 - 1 - 1 - clk self refresh exit time tsre 1 - 1 - 1 - 1 - clk 1 refresh time tref - 64 - 64 - 64 - 64 ms
rev. 1.2 / oct. 2007 12 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series command truth table command cken-1 cken cs ras cas we dqm addr a10/ap ba note mode register set h x l l l l x op code no operation h x h x x x x x l h h h bank active h x l l h h x ra v read h x l h l h x ca l v read with autopre - charge h write h x l h l l x ca l v write with autopre - charge h precharge all banks h x l l h l x x h x precharge selected bank l v burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single- write h x l l l l x a9 ball high (other balls op code) mrs mode self refresh entry h l l l l h x x exit l h h x x x x l h h h precharge power down entry h l h x x x x x l h h h exit l h h x x x x l h h h clock suspend entry h l h x x x x x l v v v exit l h x x
rev. 1.2 / oct. 2007 13 synchronous dram memory 128mbit (8mx16bit) hy57v281620f(l/s)tp series package information 400mil 54pin thin small outline package 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 22.327(0.8790) 22.149(0.8720) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 1.194(0.0470) 0.991(0.0390) 0.80(0.0315)bsc 0.400(0.016) 0.300(0.012) unit : mm(inch) 0.150(0.0059) 0.050(0.0020)

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